【公開日：2024.07.25】【最終更新日：2024.05.11】
課題データ / Project Data
課題番号 / Project Issue Number
23UT1061
利用課題名 / Title
ハイブリッド接合
利用した実施機関 / Support Institute
東京大学 / Tokyo Univ.
機関外・機関内の利用 / External or Internal Use
内部利用（ARIM事業参画者以外）/Internal Use (by non ARIM members)
技術領域 / Technology Area
【横断技術領域 / Cross-Technology Area】（主 / Main）計測・分析/Advanced Characterization（副 / Sub）-
【重要技術領域 / Important Technology Area】（主 / Main）高度なデバイス機能の発現を可能とするマテリアル/Materials allowing high-level device functions to be performed（副 / Sub）-
キーワード / Keywords
走査プローブ顕微鏡/ Scanning probe microscope,高品質プロセス材料/技術/ High quality process materials/technique,ハイブリッドボンディング/ Hybrid Bonding
利用者と利用形態 / User and Support Type
利用者名（課題申請者）/ User Name (Project Applicant)
王 俊沙
所属名 / Affiliation
先端システム技術研究組合
共同利用者氏名 / Names of Collaborators in Other Institutes Than Hub and Spoke Institutes
ARIM実施機関支援担当者 / Names of Collaborators in The Hub and Spoke Institutes
利用形態 / Support Type
（主 / Main）機器利用/Equipment Utilization（副 / Sub）-
利用した主な設備 / Equipment Used in This Project
報告書データ / Report
概要（目的・用途・実施内容）/ Abstract (Aim, Use Applications and Contents)
The present hybrid bonding of Cu/SiO2 typically includes the hydrophilic bonding of dielectric SiO2 /SiO2 and the diffusion bonding of electrical Cu/Cu. The SiO2 and Cu patterned wafers are firstly activated by N2 plasma and then contact at room temperature. To achieve the strong bonding, post-annealing at 350℃ ~ 400℃ is needed. During this process, Cu on two wafers becomes connected and are bonded through the atom diffusion. However, for the temperature-sensitive devices, the post-annealing temperature is too high. Therefore, the development of low temperature bonding is necessary.
実験 / Experimental
4 inch Cu-on-Si wafers after CMP without protective layers were vacuum-packed, and then stored in air for 3 months. To trace the surface roughness of Cu surface, L-traceⅡ (UT-861) was used and the measured area was 90 μm x 90 μm and 10 μm x 10 μm as shown in Fig.1.
結果と考察 / Results and Discussion
After CMP, the Cu surface was smooth but with some holes, and the surface roughness was Ra 0.3 nm/ Rq 0.3 nm at 10 μm x 10 μm. After vacuum-packed and stored in air for 3 months, the surface roughness of Cu-on-Si wafer center was measured both at 90 μm x 90 μm and 10 μm x 10 μm. From the result of 90 μm x 90 μm area, it can be seen the Cu surface was generally smooth with many nano-holes, and the surface roughness was Ra 1.3 nm/ RMS 2.2 nm. From the AFM image at 10 μm x 10 μm, the nano-hole on Cu surface could be clearly observed. And the Cu surface was not so smooth with the surface roughness of Ra 1.0 nm/ RMS 2.0 nm, which was much larger than the fresh CMP polished Cu surface. It means the Cu surface was oxidized by the limited air in the vacuum-packed bag. For the same wafer, the surface roughness of edge part was also measured, which was Ra 0.9 nm/ RMS 1.9 nm at 10 μm x 10 μm. The similar surface roughness of wafer center and edge parts, on the other hand, also explain the original CMP of Cu surface was uniform.
図・表・数式 / Figures, Tables and Equations
Fig. 1 Surface roughness of Cu surface after CMP for 3 months
その他・特記事項（参考文献・謝辞等） / Remarks(References and Acknowledgements)
成果発表・成果利用 / Publication and Patents
論文・プロシーディング（DOIのあるもの） / DOI (Publication and Proceedings)
口頭発表、ポスター発表および、その他の論文 / Oral Presentations etc.
特許 / Patents
特許出願件数 / Number of Patent Applications：0件
特許登録件数 / Number of Registered Patents：0件