【公開日：2024.07.25】【最終更新日：2024.05.21】
課題データ / Project Data
課題番号 / Project Issue Number
23UT1228
利用課題名 / Title
先端トランジスタの研究
利用した実施機関 / Support Institute
東京大学 / Tokyo Univ.
機関外・機関内の利用 / External or Internal Use
内部利用（ARIM事業参画者以外）/Internal Use (by non ARIM members)
技術領域 / Technology Area
【横断技術領域 / Cross-Technology Area】（主 / Main）加工・デバイスプロセス/Nanofabrication（副 / Sub）-
【重要技術領域 / Important Technology Area】（主 / Main）高度なデバイス機能の発現を可能とするマテリアル/Materials allowing high-level device functions to be performed（副 / Sub）-
キーワード / Keywords
HZO, FeFET,高品質プロセス材料/技術/ High quality process materials/technique,光リソグラフィ/ Photolithgraphy,先端半導体（超高集積回路）/ Ascanced Semiconductor (Very Large Scale Integration)
利用者と利用形態 / User and Support Type
利用者名（課題申請者）/ User Name (Project Applicant)
トープラサートポン カシディット
所属名 / Affiliation
東京大学工学系研究科電気系工学専攻
共同利用者氏名 / Names of Collaborators in Other Institutes Than Hub and Spoke Institutes
ARIM実施機関支援担当者 / Names of Collaborators in The Hub and Spoke Institutes
利用形態 / Support Type
（主 / Main）機器利用/Equipment Utilization（副 / Sub）-
利用した主な設備 / Equipment Used in This Project
報告書データ / Report
概要（目的・用途・実施内容）/ Abstract (Aim, Use Applications and Contents)
Recently, HfZrO (HZO) is the most prominent material for ferroelectric field-effect transistor (FeFET), and it is being studied a lot recently because it has strong ferroelectricity even in nm-thick scale and is capable of being used in the CMOS process currently used in industrial processes. HZO FeFET is a metal-ferroelectric-insulator-semiconductor (MFIS) 1T structure, where doping, tensile stress, thickness effect and interface state are controllable factors that can induce stronger ferroelectric properties. In order to implement an optimized HZO FeFET device, various devices are fabricated and their performances are investigated by controlling these factors. In this study, we fabricate FeFET devices by depositing HZO as a ferroelectric layer through ALD and TiN as a top gate through a sputtering system, followed by a patterning process through photolithography provided by ARIM.
実験 / Experimental
For the fabrication of FeFET, a patterning process using photolithography is essential. As equipment for this process, we utilize a mask aligner called MA6, designed for high-resolution photolithography at the micrometer scale.
結果と考察 / Results and Discussion
We successfully patterned the device through the photolithography process and completed the fabrication of the HZO FeFETs. Currently, we are determining the fundamental properties of the fabricated devices, and further exploring strategies to improve the limited endurance, a chronic problem of HZO FeFETs.
図・表・数式 / Figures, Tables and Equations
Figure 1. Microscope image (a) after exposure and development of S/D region, and (b) after lift-off process of S/D region.
その他・特記事項（参考文献・謝辞等） / Remarks(References and Acknowledgements)
成果発表・成果利用 / Publication and Patents
論文・プロシーディング（DOIのあるもの） / DOI (Publication and Proceedings)
口頭発表、ポスター発表および、その他の論文 / Oral Presentations etc.
特許 / Patents
特許出願件数 / Number of Patent Applications：0件
特許登録件数 / Number of Registered Patents：0件