【公開日：2024.07.25】【最終更新日：2024.03.21】
課題データ / Project Data
課題番号 / Project Issue Number
23AT0029
利用課題名 / Title
MoS2上ALD ZrO2ゲート絶縁膜の研究（Research of ALD ZrO2 gate dielectric on MoS2）
利用した実施機関 / Support Institute
産業技術総合研究所 / AIST
機関外・機関内の利用 / External or Internal Use
内部利用（ARIM事業参画者以外）/Internal Use (by non ARIM members)
技術領域 / Technology Area
【横断技術領域 / Cross-Technology Area】（主 / Main）加工・デバイスプロセス/Nanofabrication（副 / Sub）-
【重要技術領域 / Important Technology Area】（主 / Main）高度なデバイス機能の発現を可能とするマテリアル/Materials allowing high-level device functions to be performed（副 / Sub）-
キーワード / Keywords
成膜・膜堆積・MoS2・ALD,蒸着・成膜/ Vapor deposition/film formation,ALD,リソグラフィ/ Lithography,光リソグラフィ/ Photolithgraphy,高品質プロセス材料/技術/ High quality process materials/technique,エレクトロデバイス/ Electronic device
利用者と利用形態 / User and Support Type
利用者名（課題申請者）/ User Name (Project Applicant)
堀川 昌代
所属名 / Affiliation
産業技術総合研究所
共同利用者氏名 / Names of Collaborators in Other Institutes Than Hub and Spoke Institutes
張文馨
ARIM実施機関支援担当者 / Names of Collaborators in The Hub and Spoke Institutes
山崎 将嗣,郭 哲維,杉山 和義
利用形態 / Support Type
（主 / Main）機器利用/Equipment Utilization（副 / Sub）,技術補助/Technical Assistance
利用した主な設備 / Equipment Used in This Project
AT-006：マスクレス露光装置
AT-023：電子ビーム真空蒸着装置
AT-031：原子層堆積装置_1[FlexAL]
報告書データ / Report
概要（目的・用途・実施内容）/ Abstract (Aim, Use Applications and Contents)
To enhance the feasibility of 2-dimensional transition metal dichalcogenides (TMDCs) channels in future nano-electronic and optoelectronic devices, a top gate device structure fabricated with VLSI compatible process is mandatory. High-k dielectric ZrO2 has been directly deposited on MoS2 through low temperature atomic layer deposition (ALD) without any surface protection layer. Low capacitance equivalent thickness (CET) of ZrO2 of 2.3 nm has been achieved while maintaining the decent device performance, indicating low temperature ALD is promising for future TMDC top gate devices with high quality interface and thin CET.
実験 / Experimental
The detailed process flow for fabricating 1L MoS2 top gate MOSFETs is shown Fig 1(a). The schematic cross-section and top view of optical microscope photograph of MoS2 devices are shown in Fig. 1(b) and 1(c), respectively. Salt-assisted CVD was used to synthesize MoS2 directly on SiO2/Si substrates using MoO2 and sulfur powder. ZrO2 gate dielectrics were deposited at 150 °C thorough ALD using TEMAZ and H2O as precursors, which denotes as LT-ALD afterwards. MoS2 samples deposited with PEALD ZrO2 gate dielectrics at 300 °C were also prepared for comparison, which denotes as HT-PEALD afterwards.
結果と考察 / Results and Discussion
The impact of CET scaling on 1L MoS2 device performance was also investigated. Fig. 2(a) shows the split-CV curves at frequency of 10 kHz extracted from MoS2 nMOSFETs with LT-ALD ZrO2 gate dielectric deposited with 50 and 100 cycles, respectively. The ID-VD curves of 1L MoS2 MOSFETs with different CET were shown in Fig. 2(b). Decent device performance and reasonably small gate leakage current maintained with CET shrinking down to 2.3 nm are also shown in Fig. 2(c). Fig. 2(d) shows ID-VG hysteresis curves for 1L MoS2 devices with different CET. The gate overdrive bias was swept back and forth from -1 V to 1 V with the back-gate floating. Considerably reduced hysteresis from 280 to 155 mV despite the larger oxide field in the thin CET sample indicates the benefit of CET scaling for enhancing gate control.
図・表・数式 / Figures, Tables and Equations
Fig. 2. (a) Split-CV characteristics at frequency of 10 kHz, (b) ID-VD characteristics, (c) gate leakage curve and (d) ID-VG hysteresis curves at VD of 1 V and extracted from 1L MoS2 devices with different ALD growth cycles.
Fig. 1 (a) Process flow for fabricating MoS2 top gate MOSFETs, (b) schematic cross-section and (c) top view of optical microscope photograph of the fabricated devices.
その他・特記事項（参考文献・謝辞等） / Remarks(References and Acknowledgements)
None
成果発表・成果利用 / Publication and Patents
論文・プロシーディング（DOIのあるもの） / DOI (Publication and Proceedings)
口頭発表、ポスター発表および、その他の論文 / Oral Presentations etc.
特許 / Patents
特許出願件数 / Number of Patent Applications：0件
特許登録件数 / Number of Registered Patents：0件