The best mix and match of (1) CMOS LSI fabrication VDEC's 17-years-experienced multi-chip foundry service and (2) MEMS post-processing in cutting-edge micro/nano fabrication apparatuses installed in Federal Class 1 Supercleanroom of VDEC in Takeda Sentanchi Building provides powerful realization tools for brand-new microdevices research.
VLSI Design and Education Center, the University of Tokyo
Dr. Yoshio Mita c/o Ms. Watanabe
Takeda Buiding 301, 2-11-16, Yayoi, Bunkyo-ku, Tokyo 113-0032, Japan
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